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w25q80bw publication release date: july 30 , 201 3 - 1 - revision j 1.8v 8m - bit serial flash memory with dual and quad spi
w25q80bw - 2 - table of contents 1. general descriptions ................................ ................................ ................................ ............. 5 2. features ................................ ................................ ................................ ................................ ....... 5 3. package types ................................ ................................ ................................ ............................ 6 3.1 pin configuration soic / vsop 150 / 208 - mil ................................ ................................ ..... 6 3.2 pad configuration wson 6x5 - mm ................................ ................................ ..................... 6 3.3 pin description soic / vsop 150/208 - mil, wson 6x5 - mm ................................ ............... 6 3.4 ball configuration wl bga ................................ ................................ ................................ ... 7 3.5 ball description wl bga ................................ ................................ ................................ ...... 7 4. pin descriptions ................................ ................................ ................................ ........................ 8 4.1 chip select (/cs) ................................ ................................ ................................ .................. 8 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) ................................ .... 8 4.3 write protect (/wp) ................................ ................................ ................................ ............... 8 4.4 hold (/hold) ................................ ................................ ................................ ..................... 8 4.5 serial clock (clk) ................................ ................................ ................................ ................ 8 5. block di agram ................................ ................................ ................................ ............................ 9 6. functional descripti on ................................ ................................ ................................ ....... 10 6.1 spi operations ................................ ................................ ................................ ............. 10 6.1.1 standard spi instructions ................................ ................................ ................................ ..... 10 6.1.2 dual spi instructions ................................ ................................ ................................ ............ 10 6.1.3 quad spi instructions ................................ ................................ ................................ ........... 10 6.1.4 hold function ................................ ................................ ................................ ........................ 10 6.2 write protection ................................ ................................ ................................ ....... 11 6.2.1 write protect features ................................ ................................ ................................ .......... 11 7. status registers and instructions ................................ ................................ ............... 12 7.1 status registers ................................ ................................ ................................ ........ 12 7.1.1 busy status (bu sy) ................................ ................................ ................................ ............ 12 7.1.2 write enable latch status (wel) ................................ ................................ ......................... 12 7.1.3 block protect bits (bp2, bp1, bp0) ................................ ................................ ...................... 12 7.1.4 top/bottom block protect (tb) ................................ ................................ ............................. 12 7.1.5 sector/block protect (sec) ................................ ................................ ................................ ... 12 7.1.6 complement protect (cmp) ................................ ................................ ................................ .. 13 7.1.7 status register protect (srp 1, srp0 ) ................................ ................................ ................. 13 7.1.8 erase/program suspend status (sus) ................................ ................................ ................. 13 7.1.9 security register lock bits (lb3, lb2, lb1, lb0) ................................ ................................ 13 7.1.10 quad enable ( qe ) ................................ ................................ ................................ .............. 14 7.1.11 s tatus register memory protection (cmp = 0) ................................ ................................ ... 15 7.1.12 status register memory protection (cmp = 1) ................................ ................................ ... 16
w25q80bw publication release date: july 30 , 201 3 - 3 - revision j 7.2 instructions ................................ ................................ ................................ ................. 17 7.2.1 manufacturer and device identification ................................ ................................ ................. 17 7.2.2 instruction set table 1 (erase, program instructions) ................................ .......................... 18 7.2.3 instruction set table 2 (read instructions) ................................ ................................ ........... 19 7.2.4 instruction set table 3 (id, security instructions) ................................ ................................ . 20 7.2.5 write enable (06h) ................................ ................................ ................................ ................ 21 7.2.6 write enable for volatile status register (50h) ................................ ................................ ..... 21 7.2.7 write disabl e (04h) ................................ ................................ ................................ ............... 22 7.2.8 read status register - 1 (05h) and read status register - 2 ( 3 5h) ................................ ......... 23 7.2.9 write status register (01h) ................................ ................................ ................................ ... 23 7.2.10 read data (03h) ................................ ................................ ................................ ................. 25 7.2.11 fast read (0bh) ................................ ................................ ................................ ................. 26 7.2.12 fast read dual output (3bh) ................................ ................................ ............................. 27 7.2.13 fast read quad output (6bh) ................................ ................................ ............................ 28 7.2.14 f ast read dual i/o (bbh) ................................ ................................ ................................ ... 29 7.2.15 fast read quad i/o (ebh) ................................ ................................ ................................ . 31 7.2.16 word read quad i/o (e7h) ................................ ................................ ................................ 33 7.2.17 octal word read quad i/o (e3h) ................................ ................................ ....................... 35 7.2.18 set burst with wrap (77h) ................................ ................................ ................................ ... 37 7.2.19 continuous read mode bits (m7 - 0) ................................ ................................ .................... 38 7.2.20 continuous read mode reset (ffh or ffffh) ................................ ................................ .. 38 7.2.21 page program (02h) ................................ ................................ ................................ ........... 39 7.2.22 quad input page program ( 3 2h) ................................ ................................ ......................... 40 7.2.23 sector erase (20h) ................................ ................................ ................................ .............. 41 7.2.24 32kb block erase (52h) ................................ ................................ ................................ ...... 42 7.2.25 64kb block erase (d8h) ................................ ................................ ................................ ..... 43 7.2.26 chip erase (c7h / 60h ) ................................ ................................ ................................ ....... 44 7.2.27 erase / program suspend (75h) ................................ ................................ ......................... 45 7.2.28 erase / program resume (7ah) ................................ ................................ .......................... 46 7.2.29 power - down (b9h) ................................ ................................ ................................ .............. 47 7.2.3 0 release power - down / device id (abh) ................................ ................................ ............. 48 7.2.31 read manufacturer / device id (90h) ................................ ................................ ................. 50 7.2.32 read manufacturer / device id dua l i/o (92h) ................................ ................................ ... 51 7.2.33 read manufacturer / device id quad i/o (94h) ................................ ................................ .. 52 7.2.34 read unique id number (4bh) ................................ ................................ ........................... 53 7.2.35 read jedec id (9fh) ................................ ................................ ................................ ........ 54 7.2.36 erase security registers (44h) ................................ ................................ ........................... 55 7.2.37 progra m security registers (42h) ................................ ................................ ....................... 56 7.2.38 read security registers (48h) ................................ ................................ ............................ 57 8. electrical character istics ................................ ................................ .............................. 58
w25q80bw - 4 - 8.1 absolute maximum ratings ................................ ................................ ................................ 58 8.2 operating ranges ................................ ................................ ................................ .............. 58 8.3 power - up timing and write inh ibit threshold ................................ ................................ .... 59 8.4 dc electrical characteristics ................................ ................................ .............................. 60 8.5 ac measurement conditions ................................ ................................ ............................. 61 8.6 ac electrical characteristics ................................ ................................ .............................. 62 8.7 ac electrical characteristics (contd) ................................ ................................ ................. 63 8.8 serial output tim ing ................................ ................................ ................................ ........... 64 8.9 serial input timing ................................ ................................ ................................ .............. 64 8.10 hold timing ................................ ................................ ................................ ...................... 64 8.11 wp ti ming ................................ ................................ ................................ .......................... 64 9. package spec ification ................................ ................................ ................................ .......... 65 9.1 8 - pin soic 150 - mil (package code sn) ................................ ................................ ........... 65 9.2 8 - pin vsop 150 - mil (package code sv) ................................ ................................ .......... 66 9.3 8 - pin soic 208 - mil (package code ss) ................................ ................................ ........... 67 9.4 8 - pin vsop 208 - mil ( package code st) ................................ ................................ .......... 68 9.5 8 - pad wson 6x5 - mm (package code zp) ................................ ................................ ....... 69 9.6 8 - ball wlbga (package code by) ................................ ................................ ................... 71 10. ordering information ................................ ................................ ................................ .......... 72 10.1 valid part numbers and top side marking ................................ ................................ ........ 73 11. revision hi story ................................ ................................ ................................ ...................... 74
w25q80bw publication release date: july 30 , 201 3 - 5 - revision j 1. general description s the w25q80bw ( 8m - bit) serial flash memory provide s a storage solution for systems with limited space, pins and power. the 25 q series offers flexibility and performance well beyond ordinary ser ial flash devices. they are ideal for code shadowing to ram, executing code directly from d ua l/quad spi (xip ) and storing voice, text and data. the device operate s on a single 1.65 v to 1.95 v power supply with current consumption as low as 4ma active and 1 a for power - down. all devices are of fered in space - saving packages. the w25q80bw array is organized into 4,096 programmable pages of 256 - bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 ( 4kb sector erase), groups of 128 (32kb block erase), groups of 256 ( 64kb block erase) or the entire chip (chip erase). the w25q80bw has 25 6 erasable sectors and 1 6 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data a nd parameter storage. (see figure 2.) the w25q80bw supports the standard serial peripheral interface (spi), and a high performance d ual /quad output as well as dual/quad i/o spi: serial clock, chip select, serial data i/o 0 (di), i/o1 (do), i/o2 (/wp), and i/o3 (/hold) . spi clock frequencies of up to 80mh z are supported allowing equivalent clock rates of 160 mhz ( 80mh z x 2) for dual i/o and 320 mhz ( 80mh z x 4 ) for quad i/o when using the fast read dual /quad i/o instruction s . these transfer rates can outperform standard asynchronous 8 and 16 - bit parallel flash memories. the continuous read mode allows for efficient memory access with as few as 8 - clocks of instruction - overhead to read a 24 - bit address, allowing true xip ( execute in place) operation. a hold pin, w rite protect pin and programmable write protect ion , with top, bottom or complement array control, provide further control flexibility. additionally, the device supports jedec standard manufacturer and device identification with a 64 - bit unique serial numbe r . 2. features ? family of spiflash memories C w25q80bw : 8m - bit/ 1 m - byte ( 1 , 048 , 576 ) C 256 - byte per programmable page C standard spi: clk, /cs, di, do, /wp, /hold C dual spi: clk, /cs, io 0 , io 1 , /wp, /hold C quad spi: clk, /cs, io 0 , io 1 , io 2 , io 3 ? highest perform ance serial flash C 80mh z dual/ quad spi clocks C 160 / 320 mhz equivalent dual/quad spi C 4 0mb /s continuous data transfer rate C up to 6 x that of ordinary serial flash C more than 100,000 erase/program cycles C more than 20 - year data retention ? efficient c ontinuous read mode C low instruction overhead C continuous read with 8/16/32/64 - byte wrap C as few as 8 clocks to address memory C allows true xip ( execute in place) operation C outperforms x16 parallel flash ? low power, wide temperature range C single 1 . 65v to 1 . 95 v supply C 4 ma active current, < 1a power - down current C - 40c to +85c operating range ? flexible architecture with 4kb sectors C uniform sector erase (4k - bytes) C uniform block erase (32k and 64k - byte s ) C program one to 256 bytes C erase/progra m s uspend & resume (1) ? advanced security features C software and hardware write - protect C top/ bottom, 4kb complement array prot ection C lock - down and otp array protection C 64 - bit unique serial number for each device C 4x 256 - byte security registers with otp lock s C volatile & non - volatile status register bits ? space efficient packaging ( 2 ) C 8 - pin soic /vsop 150/208 - mil C 8 - pad wson 6x5 - mm C 8 - ball wlbga C contact winbond for kgd and other options note 1: for suspend/resume feature, please contact winbond for detailed information. 2: some package types are special orders , please contact winbond for ordering information.
w25q80bw - 6 - 3. package types w25q80bw is offered in an 8 - pin plastic 150 - mil or 208 - mil width soic (package code sn & ss) , an 8 - pin vsop 150 - mil or 208 - mil (package code sv & st), 6x5 - mm wson ( package code zp) and an 8 - ball wlbga (package code by) as shown in figure 1a - 1c respectively. package diagrams and dimensions are illustrated at the end of this datasheet. 3.1 pin configuration soic / vsop 150 / 208 - mi l figure 1 a. w25q80bw pin assignments, 8 - pin soic / vsop 150 / 208 - mil (package code sn, ss , sv, st ) 3.2 pad configuration wson 6x5 - mm figure 1 b. w25q80bw pad assignments, 8 - pad wson 6x5 - mm (package code zp) 3.3 pin de scription soic / vsop 150/208 - mil, wson 6x5 - mm pin no. pin name i/o function 1 /cs i chip select input 2 do ( io1 ) i/ o data output ( data input output 1)* 1 3 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 4 gnd ground 5 di ( io0 ) i/o data i nput ( data input output 0)* 1 6 clk i ser ial clock input 7 /hold ( io3 ) i /o hold input ( data input output 3)* 2 8 vcc power supply *1 io0 and io1 are used for standard and dual spi instructions *2 io0 C io3 are used for quad spi instructions 1 2 3 4 8 7 6 5 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view 1 2 3 4 /cs do (io 1 ) /wp (io 2 ) gnd vcc /hold (io 3 ) di (io 0 ) clk top view 8 7 6 5
w25q80bw publication release date: july 30 , 201 3 - 7 - revision j 3.4 ball configuration wl bga figure 1 c . w25q 80bw ball assignments, 8 - ball wl bga (package code by ) 3.5 ball description wl bga ball no. p in name i/o function a1 vcc power supply a2 /cs i chip select input b1 /hold ( io3 ) i /o hold input ( data input output 3)* 2 b2 do (io1) i/ o data out p ut (data input output 1)* 1 c1 clk i serial clock input c2 /wp ( io2 ) i /o write protect input ( data input output 2)* 2 d1 di ( io0 ) i /o data input (data input output 0)* 1 d2 gnd ground *1 io0 and io1 are used for standard and dual spi instructions *2 io0 C io3 are used for quad spi instructions d 1 g n d d 2 d i ( i o 0 ) a 1 / c s a 2 v c c b 1 d o ( i o 1 ) b 2 / h o l d ( i o 3 ) c 1 / w p ( i o 2 ) c 2 c l k t o p v i e w d 1 g n d d 2 d i ( i o 0 ) a 1 / c s a 2 v c c b 1 d o ( i o 1 ) b 2 / h o l d ( i o 3 ) c 1 / w p ( i o 2 ) c 2 c l k b o t t o m v i e w
w25q80bw - 8 - 4. pin descriptions 4.1 chip select ( /cs ) the spi chip select ( /cs ) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output ( do, or io0, io1, io2, i o3 ) pin s are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or write status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase t o active levels and instructions can be written to and data read from the device. after power - up, /cs must transition from high to low before a new instruction will be accepted. the /cs input must track the vcc supply level at power - up (see write protecti on and figure 3 7 ). if needed a pull - up resister on /cs can be used to accomplish this. 4.2 serial data input, output and ios (d i , d o and io0, io1, io2, io3) the w25q80bw support s standard spi, dual spi and quad spi operation. standard spi instructions use th e unidirectional d i (input) pin to serially write instructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the fall ing edge of clk. dual and quad spi instruction s use the bidirectional io pins to serially write instructions, addresses or data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. quad spi instructio ns require the non - volatile quad enable bit (qe) in status register - 2 to be set. when qe=1 , the /wp pin becomes i o 2 and /hold pin becomes io3. 4.3 write protect ( /wp ) the write protect ( /wp ) pin can be used to prevent the status register from being written. used in conjunction with the status registers block protect ( cmp, sec , tb, bp2, bp1 and bp0 ) bits and status register protect (srp) bits, a portion as small as a 4kb sector or the entire memory array can be hardware protected. the /wp pin is active low. w hen the qe bit of status register - 2 is set for q uad i/ o, the /wp pin function is not available since this pin is used for i o 2 . see figure 1a - c for the pin c onfiguration of quad i/o operation . 4.4 h old ( /hold ) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (dont care). when /hold is brought high, device operation can resume. the /hold function can be u seful when multiple devices are sharing the same spi signals. the /hold pin is active low. when the qe bit of status register - 2 is set for quad i/o, the /hold pin function is not available since this pin is used for io3. see figure 1a - b for the pin configu ration of quad i/o operation. 4.5 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input an d output operations. ("see spi operations")
w25q80bw publication release date: july 30 , 201 3 - 9 - revision j 5. block diagram figure 2 . w25q80bw serial flash memory block diagram 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 3ff00h 3ffffh ? block 3 (64kb) ? 30000h 300ffh 4ff00h 4ffffh ? block 4 (64kb) ? 40000h 400ffh ? ? ? 7ff00h 7ffffh ? block 7 (64kb) ? 70000h 700ffh 8ff00h 8ffffh ? block 8 (64kb) ? 80000h 800ffh ? ? ? fff00h fffffh ? block 15 (64kb) ? f0000h f00ffh 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh 000000h 0000ffh column decode and 256 - byte page buffer beginning page address ending page address w25q80bw spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 3 - 0 write protect logic and row decode 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 3ff00h 3ffffh ? block 3 (64kb) ? 30000h 300ffh 4ff00h 4ffffh ? block 4 (64kb) ? 40000h 400ffh ? ? ? 7ff00h 7ffffh ? block 7 (64kb) ? 70000h 700ffh 8ff00h 8ffffh ? block 8 (64kb) ? 80000h 800ffh ? ? ? fff00h fffffh ? block 15 (64kb) ? f0000h f00ffh 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh 000000h 0000ffh column decode and 256 - byte page buffer beginning page address ending page address w25q80bw spi command & control logic byte address latch / counter status register write control logic page address latch / counter do (io 1 ) di (io 0 ) /cs clk /hold (io 3 ) /wp (io 2 ) high voltage generators xx0f00h xx0fffh ? sector 0 (4kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4kb) ? xxf000h xxf0ffh block segmentation data security register 3 - 0 write protect logic and row decode
w25q80bw - 10 - 6. functional descripti on 6.1 spi operations 6.1.1 standard spi instructions the w25q80bw is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select ( /cs ), serial data input ( di ) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addresses or data to the device on the rising edge of clk . the do output pin is used to read data or status from the device on the falling edge clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 , the clk signal is normally low on t he falling and rising edges of /cs. for mode 3 , the clk signal is normally high on the falling and rising edges of /cs . 6.1.2 dual spi instructions the w25q80bw support s dual spi operation when using the fast read dual output (3bh) and fast read dual i/o (b bh) instruction s . th ese instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual spi read i nstruction s are ideal for quickly downloading code to ram upon power - up (code - shado wing) or for execut ing non - speed - critical code directly from the spi bus (xip) . when using dual spi instructions , the di and do pins become bidirectional i/ o pins: io0 and io1. 6.1.3 quad spi instructions the w25q80bw supports quad spi operation whe n using the fast read quad output (6bh) , fast read quad i/o (ebh) , word read quad i/o (e7h) and octal word read quad i/o (e3h) instructions . these instructions allow data to be transferred to or from the device six to eight times the rate of ordinary serial fla sh. the quad read instructions offer a significant improvement in continuous and random access transfer rates allowing fast code - shadowing to ram or execut ion directly from the spi bus (xip) . when using quad spi instructions the di and do pins become bidir ectional io0 and io1 , and the /wp and /hold pins become io2 and io3 respectively. quad spi instructions require the non - volatile quad enable bit (qe) in status register - 2 to be set . 6.1.4 hold function for standard spi and dual spi operations, t he /hold signal a llows the w25q80bw operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only parti ally written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. the /hold func tion is only available for standard spi and dual spi operation, not during quad spi. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is alrea dy low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold
w25q80bw publication release date: july 30 , 201 3 - 11 - revision j condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, a nd serial data input (di ) and serial clock (clk) are ignored. the chip select ( /cs ) signal should be kept active low for the full duration of the /hold operation to avoid resetting the internal logic state of the device. 6.2 write protection applications that use non - volatile memory must take into consideration the possibility of noise and other adverse system conditions that ma y compromise data integrity. to address this concern , the w25q80bw provides several means to protect the data from inadvertent writes. 6.2.1 write protect features ? device resets when vcc is below threshold ? time delay write disable after power - up ? write enable/di sable instructions and a ut omatic write disable after e rase or program ? software and hardware (/wp pin) write protection using status register ? write protection using power - down instruction ? lock down write protection until next power - up ? one time program (ot p) write protection * * note : this feature is available upon special order. please contact winbond for details. upon power - up or at power - down , the w25q80bw will maintain a reset condition while vcc is below the threshold value of v wi , (see power - up timin g and voltage levels and figure 3 7 ). while reset, all operations are disabled and no instructions are recognized. during power - up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t pu w . this includes the write enable, page program, sector erase, block erase, chip erase and the write status register instructions. note that the chip select pin ( /cs ) must track the vcc supply level at power - up until the vcc - min level and t vsl time delay i s reached. if needed a pull - up resister on /cs can be used to accomplish this. after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be iss ued before a page program, sector erase, block erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write - disabled state o f 0. software controlled write protection is facilitated using the write status register instruction and setting the status register protect (srp 0, srp1 ) and block protect ( cmp, sec, tb, bp2, bp1 and bp0 ) bits. these settings allow a portion as small as 4kb sector or the entire memory array to be configured as read only. used in conjunction with the write protect ( /wp ) pin, changes to the status register can be enabled or disabled under hardware control. see status register section for further information. a dditionally, the power - down instruction offers an extra level of write protection as all instructions are ignored except for the release power - down instruction.
w25q80bw - 12 - 7. status registers and instructions the read status register - 1 and status register - 2 instruction s can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, t he state of write protection , quad spi s e tting , security register lock status and erase/program suspend status . the write status reg ister instruction can be used to configure the device write protection features , quad spi sett i ng and security register otp lock . write access to the status register is controlled by the state of the non - volatile s tatus register protect bits (srp 0, srp1 ) , the write enable instruction, and during standard/dual spi operations, the /wp pin . 7.1 status register s 7.1.1 busy status (busy) busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, quad page pro gram, sector erase, block erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further instructions except for the read status register and erase /program suspend instruction (see t w , t pp , t se , t b e , and t c e in ac characteristics). when the program, erase or write status /security register instruction has completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. 7.1.2 write enable latch st atus (wel) write enable latch (wel) is a read only bit in the statu s register (s1) that is set to 1 after executing a write enable instruction. th e wel status bit is cleared to 0 when the device is write disabled. a write disable state occurs upon power - up or after any of the following instructions: write disable, page program, quad page program, sector erase, block erase, chip erase, write status register , erase security register and program security register . 7.1.3 block protect bits (bp2, bp1, bp0) the block p rotect bits (bp2, bp1, bp0 ) are non - volatile read/write bits in the status register (s4, s3, and s2 ) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. 7.1.4 top/bottom block p rotect (tb) the non - volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the f actory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 7.1.5 sector /block protect (sec) the non - volatile sector /block p rotect bit (sec) controls if the block protect bits (bp2, bp1, bp0) protect either 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the default setting is sec =0.
w25q80bw publication release date: july 30 , 201 3 - 13 - revision j 7.1.6 complement protect (cmp) the c omplement p rotect bit (cmp) is a non - volatile read/write bit in the status register (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 4kb sector can be protected while the rest of the array is not; when cmp=1, the top 4kb sector will become unprotected while the rest of the array become read - only. please refer to the status register memory pr otection table for details. the default setting is cmp =0. 7.1.7 status register protect (srp 1 , srp 0 ) the status register protect bits (srp 1 and srp0 ) are non - volatile read/write bits in the status register (s8 and s7). the srp bits control the method of write p rotection: s oftware p rotection, h ardware p rotection, p ower s upply l ock - d own or o ne t ime p rogrammable (otp) p rotection. srp1 srp0 /wp status register description 0 0 x software protection /wp pin has no control. the status register can be written to after a write enable instruction , wel=1 . [factory default] 0 1 0 hardware protect ed when /wp pin is low the status register locked and can not be written to . 0 1 1 hardware unprotected when /wp pin is high the status register is unlocked and can be written t o after a write enable instruction , wel=1. 1 0 x power supply lock - down status register is protected and can not be written to again until the next power - down , power - up cycle . ( 1 ) 1 1 x one time program ( 2 ) status register is permanently protected and ca n not be written to. note s : 1. when srp1, srp0 = (1, 0), a power - down, power - up cycle will change srp1, srp0 to (0, 0) state. 2 . this feature is available upon special order. please contact winbond for details. 7.1.8 erase/program suspend status (sus) the sus pend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase/program suspend (75h) instruction. the sus status bit is cleared to 0 by erase/program resume (7ah) instr uction as well as a power - down, power - up cycle . 7.1.9 security register lock bits (lb3, lb2, lb1 , lb0) the security register lock bits (lb3, lb2, lb1, lb0) are non - volatile one time program (otp) bits in status register (s13, s12, s11, s10) that provide the write protect control and status to the security r egisters . the default state of lb3 - 0 is 0, security registers are unlocked. lb3 - 0 can be set to 1 individually using the write status register instruction. lb3 - 0 are one time programmable (otp), once its set to 1, the corresponding 256 - byte security regis ter will become read - only permanently.
w25q80bw - 14 - 7.1.10 quad enable ( qe ) the quad enable (qe ) bit is a non - volatile read/write bit in the status register (s 9 ) that allow s quad spi operation . when the qe bit is set to a 0 state (factory default) , the /wp pin and /h old are e nabled . when the qe bit is set to a 1 , the quad io2 and i o3 pins are enabled , and /wp and /hold functions are disabled . warning: i f the /wp or /hold pins are tied directly to the power supply or ground during standard spi or dual spi operation , t he qe bit should never be set to a 1 . figure 3 a . status register - 1 figure 3 b . status register - 2 s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non - volatile) sector protect (non - volatile) top/bottom protect (non - volatile) block protect bits (non - volatile) write enable latch erase/write in progress s7 s6 s5 s4 s3 s2 s1 s0 srp0 sec tb bp2 bp1 bp0 wel busy status register protect 0 (non - volatile) sector protect (non - volatile) top/bottom protect (non - volatile) block protect bits (non - volatile) write enable latch erase/write in progress s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 lb0 qe srp1 suspend status complement protect (non - volatile) security register lock bits (non - volatile otp) quad enable (non - volatile) status register protect 1 (non - volatile) s15 s14 s13 s12 s11 s10 s9 s8 sus cmp lb3 lb2 lb1 lb0 qe srp1 suspend status complement protect (non - volatile) security register lock bits (non - volatile otp) quad enable (non - volatile) status register protect 1 (non - volatile)
w25q80bw publication release date: july 30 , 201 3 - 15 - revision j 7.1.11 status register memory protection (cmp = 0) status register (1) w25q80bw ( 8 m - bit) memory protecti on (2 ) sec tb bp2 bp1 bp0 block(s ) addresses density portion x x 0 0 0 none none none none 0 0 0 0 1 15 0 f0000h C 0 fffffh 64kb upper 1/16 0 0 0 1 0 14 and 15 0 e0000h C 0 fffffh 128kb upper 1/8 0 0 0 1 1 12 thru 15 0 c0000h C 0 fffffh 256kb upper 1/4 0 0 1 0 0 8 thru 15 0 80000h C 0 fffffh 512kb upper 1/2 0 1 0 0 1 0 000000h C 00ffffh 64kb lower 1/16 0 1 0 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/8 0 1 0 1 1 0 thru 3 000000h C 03ffffh 256kb lower 1/4 0 1 1 0 0 0 thru 7 000000h C 07ffffh 512kb lower 1/2 0 x 1 0 1 0 thru 15 000000h C 0f ffffh 1mb all 0 x 1 1 x 0 thru 15 000000h C 0f ffffh 1mb all 1 0 0 0 1 15 0ff000 h C 0f ffffh 4kb upper 1 /256 1 0 0 1 0 15 0fe000 h C 0f ffffh 8kb upper 1 /128 1 0 0 1 1 15 0fc000 h C 0f ffffh 16kb upper 1 /64 1 0 1 0 x 15 0f8000 h C 0f ffffh 32kb upper 1/32 1 1 0 0 1 0 000000h C 000fffh 4kb lower 1 /256 1 1 0 1 0 0 000000h C 001fffh 8kb lower 1 /128 1 1 0 1 1 0 000000h C 003fffh 16kb lower 1 /64 1 1 1 0 x 0 000000h C 007fffh 32kb lower 1/32 1 x 1 1 1 0 thru 15 000000h C 0f ffffh 1mb all note s : 1. x = don t care 2. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
w25q80bw - 16 - 7.1.12 status register memory protection (cmp = 1) status register (1) w25q80bw ( 8 m - bit) memory protecti on (2 ) sec tb bp2 bp1 b p0 block(s) addresses density portion x x 0 0 0 0 thru 15 000000h C 0f ffffh 1mb all 0 0 0 0 1 0 thru 14 0 0 0000h C 0 e ffffh 960 kb lower 1 5 /16 0 0 0 1 0 0 thru 1 3 0 0 0000h C 0 d ffffh 896 kb low er 7 /8 0 0 0 1 1 0 thru 1 1 0 0 0000h C 0 b ffffh 768 kb low er 3 /4 0 0 1 0 0 0 thru 7 0 0 0000h C 0 7 ffffh 512kb low er 1/2 0 1 0 0 1 1 thru 15 0 1 0000h C 0 f ffffh 960 kb upp er 1 5 /16 0 1 0 1 0 2 thru 15 020000h C 0fffffh 896kb upper 7/8 0 1 0 1 1 4 thru 15 040000h C 0fffffh 768kb upper 3/4 0 1 1 0 0 8 thru 15 080000h C 0fffffh 512kb upper 1/2 0 x 1 0 1 none none none none 0 x 1 1 x none none none none 1 0 0 0 1 0 thru 15 0 00 000 h C 0f efffh 1,020 kb lower 255/256 1 0 0 1 0 0 thru 15 0 00 000 h C 0f dfffh 1,016 kb lower 127/128 1 0 0 1 1 0 thru 15 0 00 000 h C 0f bfffh 1,008 kb lower 63 /64 1 0 1 0 x 0 thru 15 0 00 000 h C 0f 7fffh 99 2kb lower 31/32 1 1 0 0 1 0 thru 15 00 1 000h C 0 ff fffh 1,020 kb upper 255/256 1 1 0 1 0 0 thru 15 00 2 000h C 0 ff fffh 1,016 kb upper 127/128 1 1 0 1 1 0 thru 15 00 4 000h C 0 ff fffh 1,008 kb upper 63/64 1 1 1 0 x 0 t hru 15 00 8 000h C 0 ff fffh 99 2kb upper 31/32 1 x 1 1 1 none none none none note s : 1. x = dont care 2. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
w25q80bw publication release date: july 30 , 201 3 - 17 - revision j 7.2 instructions the instruction set of the w25q80bw consists of thirty f our basic instructions that are fully controlled through the spi bus (see instruction set table 1 - 3 ). instructions are initiated with the falling edge of chip select (/cs) . the first byte of data clo cked into the di i nput provides the i nstruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs . clock relative timing diagrams for each instruction are included in figures 4 through 3 6 . all read instructions can be completed after any cl ocked bit. however, all instructions that write, program or erase must complete on a byte boundary ( / cs driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignor ed. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except for read status register will be ignored until the program or erase cycle has completed. 7.2.1 manufacturer and device ide ntification manufacturer id (m f 7 - m f 0) winbond serial flash ef h device id (id7 - id0) (id15 - id0) instruction abh, 90h , 92h, 94h 9fh w25q80bw 1 3 h 5 014h
w25q80bw - 18 - 7.2.2 instruction set table 1 (erase, program instructions) ( 1 ) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 write enable 06h write enable for volatile status register 50h write disable 04h read status register - 1 05h (s7 C s0) ( 2 ) read status register - 2 35h (s 15 C s 8 ) ( 2 ) write status register 01h s7 C s0 s 15 - s8 page program 02h a23 C a16 a15 C a8 a7 C a0 d7 C d0 quad page program 3 2h a23 C a16 a15 C a8 a7 C a0 d7 C d0 , (3) sector erase (4kb) 20h a23 C a16 a15 C a8 a7 C a0 block erase (32kb) 52h a23 C a16 a15 C a8 a7 C a0 block erase (64kb) d8h a23 C a16 a15 C a8 a7 C a0 chip erase c7h /60h erase / program suspend (5) 75h erase / program resume (5) 7ah power - down b9h continuous read mode reset (4) ffh ffh notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis () indicate data being read from th e device on the do pin. 2. the status register contents will repeat continuously until /cs terminates the instruction. 3. quad page program input data : io0 = d4, d0, io1 = d5, d1, io2 = d6, d2, io3 = d7, d3, 4. this instruction is recommended w hen using the dual or quad continuous read mode feature. see section 7.2 . 1 9 & 7.2 . 20 for more information. 5. for suspend/resume feature, please contact winbond for detailed information.
w25q80bw publication release date: july 30 , 201 3 - 19 - revision j 7.2.3 instruction set table 2 ( read ins tructions) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) fast read dual output 3bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (1) fast read quad output 6bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0 , ) (3) fast read dual i/o bbh a23 - a 8 (2) a7 - a0, m7 - m0 (2) (d7 - d0 , ) (1) fast read quad i/o ebh a23 - a0, m7 - m0 (4) ( x,x,x,x, d7 - d0 , ) (5) (d7 - d0, ) (3) word read quad i/o (7) e7h a23 - a0, m7 - m0 (4) ( x,x, d7 - d0 , ) (6) (d7 - d0, ) (3) octal word read quad i/o (8) e3h a23 - a0, m7 - m0 (4) (d7 - d0, ) (3) set burst with wrap 77h xxxxxx , w 6 - w 4 (4) notes : 1 . dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2 . dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3 . quad output data io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 4 . quad input address set burst with wrap input io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x , x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 5 . fast read quad i/o data io0 = (x, x, x, x, d4, d0, ..) io1 = (x, x, x, x, d5, d1, ..) io2 = (x, x, x, x, d6, d2, ..) io3 = (x, x, x, x, d7, d3, .. ) 6. word read quad i/o data io0 = (x, x, d4, d0, ..) io1 = (x, x, d5, d1, ..) io2 = (x, x, d6, d2, ..) io3 = (x, x, d7, d3, ..) 7 . the lowest address bit must be 0. ( a0 = 0 ) 8. the lowest 4 address bits must be 0. ( a0, a1, a2, a3 = 0 )
w25q80bw - 20 - 7.2.4 instruc tion set table 3 (id, security instructions) instruction name byte 1 ( code ) byte 2 byte 3 byte 4 byte 5 byte 6 release power down / device id abh dummy dummy dummy (id7 - id0) (1) manufacturer/ device id ( 2 ) 90h dummy dummy 00h (mf7 - mf0) (id7 - id0) manufact urer/device id by dual i/o 92h a23 - a8 a7 - a0, m[7:0] (mf[7:0], id[7:0]) manufacture/device id by quad i/o 94h a23 - a0, m[7:0] xxxx, (mf[7:0], id[7:0]) (mf[7:0], id[7:0], ) jedec id 9fh (mf7 - mf0) manufacturer (id15 - id8) memory type (id7 - id0) capacity read unique id 4bh dummy dummy dummy dummy (id63 - id0) erase security registers (3) 44h a23 C a16 a15 C a8 a7 C a0 program security registers (3) 42h a23 C a16 a15 C a8 a7 C a0 d7 - d 0 d7 - d 0 read security registers (3) 48h a23 C a16 a15 C a8 a7 C a0 dummy (d7 - 0) notes: 1. the device id will repeat continuously until /cs terminates the instruction. 2. see manufacturer and device identification table for device id information. 3. security register address: security register 0: a23 - 16 = 00h ; a15 - 8 = 00h ; a7 - 0 = byte address secur ity register 1 : a23 - 16 = 00h ; a15 - 8 = 10h ; a7 - 0 = byte address security register 2 : a23 - 16 = 00h ; a15 - 8 = 20h ; a7 - 0 = byte address security register 3 : a23 - 16 = 00h ; a15 - 8 = 30h ; a7 - 0 = byte address please note that security register 0 is reserve d by winbond for future use. it is recommended to use security registers 1 - 3 before using register 0
w25q80bw publication release date: july 30 , 201 3 - 21 - revision j 7.2.5 write enable (06 h) the write en able instruction (figure 4 ) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, quad page program, sector erase, block erase , chip erase, write status register and erase/program security registers instruction. the write enable instruction is entered by driving /cs low, shifting the instruction code 06h i nto the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 4. write en able instruction sequence diagram 7.2.6 write enable for volatile status register (50h) t he non - volatile status register b it s describ ed in section 8 .1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection scheme s quickly without waiting for the typical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a write status register (01h) instruction. write enable for volatile stat us register instruction (figure 5) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit value s . figure 5. write enable for volatil e status register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance
w25q80bw - 22 - 7.2.7 write disable (04 h) the write dis able instruction (figure 6 ) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the ins tructio n code 04h into the di pin and then driving /cs high. note that the wel bit is automatically reset after power - up and upon completion of the write status register, erase/program security registers, page program, quad page program, sector erase, bl ock erase and chip erase instructions. write disable instruction can also be used to invalidate the write enable for volatile status register instruction. figure 6 . write dis able instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance
w25q80bw publication release date: july 30 , 201 3 - 23 - revision j 7.2.8 read status regist er - 1 (05h) and read status register - 2 ( 3 5h) the read status register instruction s allow the 8 - bit status register s to be read. the instruction is entered by driving /cs low and shifting the instruction code 05h for status r egister - 1 or 35h for status r egister - 2 into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 7 . the status register bits are shown in figure 3 a and 3b and include the busy, wel, bp 2 - bp 0 , tb , sec, srp0, srp1 , qe , lb3 - 0, cmp and sus bits (see status register section earlier in this datasheet ). the read status register instruction may be used at any time, even while a program, erase or write status registe r cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the status register can be read continuously, as shown in figure 7 . the instruction is completed by driving /cs high. figure 7 . read status register instruction sequence diagram 7.2.9 write status register (01h) the write status register instruction allows the status register to be written. only non - volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7 thru 2 of status register - 1) and cmp, lb3, lb2, lb1, lb0, qe, srp1 (bits 14 thru 8 of status register - 2) can be written to. all other status register bit locations are read - only and will not be affected by the write status register instruction . lb3 - 0 are non - volatile otp bits, once it is set to 1, it can not be cleared to 0. the status register bits are shown in figure 3 a and 3b and described in 8 .1 . to write non - volatile status register bits, a standard write enable (06h) instruction must prev iously have been executed for the device to accept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code 01h, and then writing the sta tus register data b yte as illustrated in figure 8 . to write volatile status register bits, a write enable for volatile status register (50h) instruction must have been executed prior to the wr ite status register instruction (status register bit wel remains 0). however, srp1 and lb3, lb2, lb1, lb0 can not be changed from 1 to 0 because of the otp protection for these bits. upon power off, the volatile status register bit values will be lost, and the non - volatile status register bit values will be restore d when power on again. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (05h or 35h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 status register 1 or 2 out status register 1 or 2 out * * = msb *
w25q80bw - 24 - to complete the write status register instruction, t he /cs pin must be driven high after the eighth or sixteenth bit of data that is clocked in. if this is not done the write status register instruction will not be executed. if /cs is driven high after the eighth clock (compatible with the 25x series) the cmp, qe and srp1 bits will be cleared to 0. during non - volatile status register write operation (06h combined with 01h), a fter /cs is driven high, the self - timed write status regist er cycle will commence for a time duration of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write status register cycle has finished , the write enable latch (wel) bit in the status register will be cleared to 0. during volatile s tatus register write operation (50h combined with 01h), after /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shs l2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. please refer to 8 .1 for detailed status register bit descriptions . factory default for all status register bits are 0. figure 8 . write status register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb *
w25q80bw publication release date: july 30 , 201 3 - 25 - revision j 7.2.10 read data (03h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h followed by a 24 - b it address (a23 - a0) into the di pin. the code and add ress bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automa tically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is c ompleted by driving /cs high. the read data instruction sequence is shown in figure 9 . if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the curren t cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 9 . read data instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
w25q80bw - 26 - 7.2.11 fast read (0bh) the fast read instruction is similar to t he read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 10 . the dummy clocks allow the devices internal circuits additional time for setting up the initial address. during the dummy clocks the data value on the d o pin is a dont care. figure 10 . fast read instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
w25q80bw publication release date: july 30 , 201 3 - 27 - revision j 7.2.12 fast read dual output (3bh) the fast read dual out put (3bh) instruction is similar to the standard fast read (0bh) instruction except th at data is output on two pins ; i o 0 and io 1 . this allows data to be transferred from the w25q80bw at twice the rate of standard spi devices. the fast read dual output inst ruction is ideal for quickly downloading code from flash to ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possibl e frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 1 1 . the dummy clocks allow the device's internal circuits additional time for setting up the initial addr ess. the input data during the dummy clocks is dont care. however, the io 0 pin should be high - impedance prior to the falling edge of the first data out clock. figure 1 1 . fast read dual output instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
w25q80bw - 28 - 7.2.13 f ast read quad output (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . a quad enable of status register - 2 must be executed before th e device will accept the fast read quad output instruction (status register bit qe must equal 1 ) . the fast read quad output instruction allows data to be transferred from the w25q80bw at four times the rate of stan dard spi devices. t he fast read q ua d outp ut instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 1 2 . the dummy clocks allow the device's internal circuit s additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io pins should be high - impedance prior to the falling edge of the first data out clock. figure 1 2 . fast read quad output instruct ion sequence diagram /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
w25q80bw publication release date: july 30 , 201 3 - 29 - revision j 7.2.14 f ast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23 - 0) two bits per clock. this reduced instruction overhead may allow for code execution (xip) directly from the d ua l spi in some applications. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further reduce instruction overhead through setting the co ntinuous read mode b its (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 3 a . the upper nibble of the (m7 - 4) controls the length of the next fast read dual i/o instruction through t he inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bit s m 5 - 4 = (1, 0 ) , then the next fast read dual i/o instruction ( after /cs is raised and then lowered) does not require the bbh instruction code, as shown in figure 1 3 b. this reduces the instruction sequence by eight clocks and allows the read address to be im mediately entered after /cs is asserted low. if the continuous read mode bit s m 5 - 4 do not equal to ( 1 ,0) , the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continu ous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7.2 . 20 for detail descriptions). figure 1 3 a . fast read dual i / o instruction sequence ( initial instruction or previous m 5 - 4 ? 1 0 ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
w25q80bw - 30 - figure 1 3 b . fast read dual i / o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 15 /cs clk di (io 0 ) do (io 1 ) 0 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 0 1 2 3 4 5 6 7 16 17 18 20 21 22 19 23 * = msb *
w25q80bw publication release date: july 30 , 201 3 - 31 - revision j 7.2.15 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and outpu t through four pins io 0 , io 1 , io 2 and io 3 and four dummy clock are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad e nable bit (qe) of status register - 2 must be set to enable the fast r ead quad i/o instruction . fast read quad i/o with continuous read mode the fast read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bit s (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 4 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bit s of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bit s m 5 - 4 = (1, 0 ) , then the next fast read quad i/o instruction ( after /cs is raised a nd then lowered) does not require the ebh instruction code, as shown in figure 1 4 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bit s m 5 - 4 do not equal to ( 1 ,0) , the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing n ormal instructions (see 7.2 . 20 for detail descriptions). figure 1 4 a . fast read quad i / o instruction sequence ( initial instruction or previous m 5 - 4 ? 1 0 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
w25q80bw - 32 - figure 1 4 b . fast read quad i / o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) fast read quad i/o with 8/16/32/64 - byte wrap around the fast read quad i/o instruction can also be used to access a specific portion within a page by issui ng a set burst with wrap command prior to ebh . the set burst with wrap command can either enable or disable the wrap around feature for the following ebh commands . when wrap around is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automati cally until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows three wrap bits, w6 - 4 to be set . the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap around section within a page. see 7.2 .1 8 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 dummy dummy
w25q80bw publication release date: july 30 , 201 3 - 33 - revision j 7.2.16 word read quad i/o (e7h) the word read quad i/o (e 7 h) instruction is similar to the fast read quad i/o ( e bh) instruction except that the lowest a ddress bit (a0) must equal 0 and only two dummy clock are required prior to the data output . the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad e nable bit (qe) of status register - 2 must be set to enable the word r ead quad i/o instru ction . word read quad i/o with continuous read mode the word read quad i/o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 5 a . the upper nibble of the (m7 - 4) controls the length of the next fast read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedan ce prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the e7h instruction code, as shown in figure 1 5 b. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowe red) requires the first byte instruction code, thus returning to normal operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7.2 . 20 for detail descriptions). figure 1 5 a . word read quad i / o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 dummy instruction (e7h)
w25q80bw - 34 - figure 1 5 b . word read quad i / o instruction sequence ( previous in struction set m 5 - 4 = 1 0 ) word read quad i/o with 8/16/32/64 - byte wrap around the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap command prior to e7h. the set burst with wrap command can either enable or disable the wrap around feature for the following e7h commands. when wrap around is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64 - byte section of a 256 - byte page. the output data starts at th e initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruction allows three w rap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap around section within a page. see 7.2 .18 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 dummy
w25q80bw publication release date: july 30 , 201 3 - 35 - revision j 7.2.17 octal word read quad i/o (e3h) the octa l word read quad i/o (e3h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1 , a2, a3 ) must equal 0. as a result, the dummy clocks are not required, which further reduces the instruction overh ead allowing even faster random access for code execution (xip). the quad enable bit (qe) of status register - 2 must be se t to enable the octal word r ead quad i/o instruction. octal word read quad i/o with continuous read mode the octal word read quad i/ o instruction can further reduce instruction overhead through setting the continuous read mode bits (m7 - 0) after the input address bits (a23 - 0), as shown in figure 1 6 a. the upper nibble of the (m7 - 4) controls the length of the next octal word read quad i /o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the io pins should be high - impedance prior to the falling edge of the first data out clock. if the con tinuous read mode bits m5 - 4 = (1,0), then the next fast read quad i/o instruction ( after /cs is raised and then lowered) does not require the e3h instruction code, as shown in figure 1 6b. this reduces the instruction sequence by eight clocks and allows th e read address to be immediately entered after /cs is asserted low. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction ( after /cs is raised and then lowered) requires the first byte instruction code, thus returning to norma l operation. a continuous read mode reset instruction can also be used to reset (m7 - 0) before issuing normal instructions (see 7.2 . 20 for detail descriptions). figure 1 6 a. octal word read quad i/o instruction sequence ( initial instruction or previous m 5 - 4 ? 10 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 instruction (e3h) 4 0 5 1 6 2 7 3 byte 4
w25q80bw - 36 - figure 1 6 b. octal word read quad i/o instruction sequence ( previous instruction set m 5 - 4 = 1 0 ) m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 4 0 5 1 6 2 7 3 a15-8 a7-0 4 0 5 1 6 2 7 3 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 5 6 7 ios switch from input to output byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 byte 4
w25q80bw publication release date: july 30 , 201 3 - 37 - revision j 7.2.18 set burst with wrap (77h) the set burst with wrap (77h) instruction is used in conjun ction with fast read quad i/o and word read quad i/o instructions to access a fixed length of 8/16/32/64 - byte section within a 256 - byte page. certain applications can benefit from this feature and improve the overall system code execution performance. similar to a quad i/o instruction, the set burst wit h wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24 dummy bit s and 8 wrap bits , w7 - 0 . the instruction sequence is shown in figure 17. wrap bit w7 and the lower nibble w3 - 0 are not used. w 6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - byte no n/a once w6 - 4 is set by a set burst with wrap instruction, all the following fa st read quad i/o and word read quad i/o instructions will use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on is 1. in the case of a system reset while w4 = 0, it is recommended that the controller issues a set burst with wrap instruction to reset w4 = 1 prior to any normal read instructions since w25q 80bw does not have a hardware reset pin . figure 17. set burst with wrap instruction sequence wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
w25q80bw - 38 - 7.2.19 continuous read mode bits (m7 - 0) the continuous read mode bits are used in conjunction with fast read dual i/o, fast read quad i/o, word read quad i/o and octal word read quad i/o instructions to provide the highest random flash memory access rate with minimum spi instruction overhead, thus allow true xip (execute in place) to be performed on serial flash devices. m7 - 0 need to be set by the dual/quad i /o read instructions. m 5 - 4 are used to control whether the 8 - bit spi instruction code (bbh, ebh, e7h or e3h) is needed or not for the next command. when m 5 - 4 = (1, 0 ) , the next command will be treated same as the current dual/quad i/o read command without n eeding the 8 - bit instruction code; when m 5 - 4 do not equal to (1,0) , the device returns to normal spi mode, all commands can be accepted. m7 - 6 and m3 - 0 are reserved bits for future use, either 0 or 1 values can be used. 7.2.20 continuous read mode reset (ffh or ff ffh) continuous read mode reset instruction can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation , as shown in figure 18. figure 1 8 . continuous read mode reset for fast read dual/quad i/o since w25q80bw does not have a hardware reset pin, so if the controller resets while w25q80bw is set to continuous mode read, the w25q80bw will not recognize any initial standard spi instructions from the controller . to address this possibility, it is recommended to issue a continuous read mode reset instruction as the first instruction after a system reset. doing so will release the device from the continuous read mode and allow standard spi instructions to be recognized. to reset continuous read mode during quad i/o operation, only eight clocks are needed. the instruction is ffh. to reset continuous read mode during dual i/o operation, sixteen clocks are needed to shift in instruction ffffh. /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 don't care 6 7 8 9 10 11 12 13 14 15 mode bit reset for quad i/o (ffh) mode 0 mode 3 mode bit reset for dual i/o (ffffh) don't care don't care
w25q80bw publication release date: july 30 , 201 3 - 39 - revision j 7.2.21 pa ge program (02h) the page pro gram instruction allows from one byte to 256 bytes ( a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit we l = 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h followed by a 24 - bit address (a23 - a0) and at l east one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 1 9 . if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same pa ge. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent dat a. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /cs is driven high, the self - timed page progra m instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page program i nstruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits . figure 1 9 . page program instruction sequence diagram /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q80bw - 40 - 7.2.22 quad input page program ( 3 2h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applications that have slow clo ck speeds <5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock - in the data. to use quad page program the quad enable i n status register - 2 must be set (qe=1). a write enable instruction must be executed before the device will accept the quad page program instruction (status register - 1, wel=1). the instruction is initiated by driving the /cs pin low then shifting the instru ction code 32h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 20 . figure 20 . quad input page program instruction sequence diagram /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
w25q80bw publication release date: july 30 , 201 3 - 41 - revision j 7.2.23 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low a nd shifting the instruction code 20h followed a 24 - bit sector address (a23 - a0) (see figure 2). the sector erase instructi on sequence is shown in figure 2 1 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self - timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status r egister instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector era se cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status regi ster memory protection table). figure 2 1 . sector erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q80bw - 42 - 7.2.24 32kb block erase (52h) the block erase instruction sets all memory within a specified block ( 32 k - bytes) to the erased state of all 1s (ffh) . a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 52 h followed a 24 - bi t block address (a23 - a0) (see figure 2). the block erase instructio n sequence is shown in figure 2 2 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be execute d. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 2 2 . 32kb block erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q80bw publication release date: july 30 , 201 3 - 43 - revision j 7.2.25 64kb block erase (d8h) the block erase instruction sets all memory within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the bloc k erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code d8h followed a 24 - bit block address (a23 - a0) (see figure 2). the block erase instructio n sequence is sho wn in figure 2 3 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence fo r a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status register memory protection table). figure 2 3 . 64kb block erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q80bw - 44 - 7.2.26 chip erase (c7h / 60h ) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is i nitiated by driving the /cs pin low and shifting the instruction code c7h or 60h . the chip erase instructio n sequence is shown in figure 2 4 . the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instr uction will not be executed. after /cs is driven high, the self - timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be acc essed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect ( cmp, sec, tb, bp2, bp1, and bp0 ) bits (see status register memory protection table). figure 2 4 . chip erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3
w25q80bw publication release date: july 30 , 201 3 - 45 - revision j 7.2.27 erase / program s uspend (75h) the erase/program suspend instruction 75h, allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program/erase data to, any other sectors or blocks. the erase/program suspend instruction sequence is shown in figure 25. please contact winbond for detailed information if this feature is required for a specific design. figure 2 5 . erase /program sus pend instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
w25q80bw - 46 - 7.2.28 erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an erase/program suspend. please contact winbond for deta iled information if this feature is required for a specific design. figure 2 6 . erase /program resume instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase
w25q80bw publication release date: july 30 , 201 3 - 47 - revision j 7.2.29 power - down (b9h) although the standby current during normal operation is relatively low, standby curren t can be further reduced with the power - down instruction. the lower power consumption makes the power - down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as shown in figure 2 7 . the /cs pin must be driven high after the eighth bit has been latched. if this is not done the power - down instruction will not be executed. after /cs is driven high, the power - dow n state will entered within the time duration of t dp (see ac characteristics). while in the power - down state only the release from power - down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. the device always pow ers - up in the normal operation with the standby current of icc1. figure 2 7 . deep power - down instruction sequence diagram /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current
w25q80bw - 48 - 7.2.30 release power - down / device id (abh) the release from power - down / device id instruction is a multi - purpose instruction. it can be used to release the d evice from the power - down state , or obtain the devices electronic ident ification (id) number . to release the device from the power - down state, the instruction is issued by driving the /cs pin low, shifti ng the instruction code abh and driving /cs high as shown in figure 2 8 a . release from power - down will take the time duration of t res 1 (see ac characteristics) before the device will resume normal operation and other instructions are accepted. the /cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code abh followed by 3 - dummy bytes. the devic e id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 2 8 a . the d evice id values for the w25q80bw is listed in manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power - down state and obtain the device id, the instruction is the same as previously described, and shown in figure 2 8 b , except that after /cs is driven high it mu st remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power - down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle . figure 2 8 a . release power - down instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current
w25q80bw publication release date: july 30 , 201 3 - 49 - revision j figure 2 8 b . release power - down / device id instruction sequence diagram tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb *
w25q80bw - 50 - 7.2.31 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power - down / device id instruction that provides both the j edec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruct ion code 90h followed by a 24 - bit address (a23 - a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit ( msb) first as shown in figure 29 . the device id valu es fo r the w25q80bw is listed in manufacturer and device identification table. if the 24 - bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuo usly, alternating from one to the other. the instruction is completed by driving /cs high. figure 29 . read manufacturer / device id diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
w25q80bw publication release date: july 30 , 201 3 - 51 - revision j 7.2.32 read manufacturer / device id dual i/o (92h) the manufacturer / device id dual i/o instruction is an alternativ e to the read manufacturer/device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufactur er / device id dual i/o instruction is similar to the fast read dual i/o instruction. the inst ruction is initiated by driving the /cs pin low and shifting the instruction code 9 2 h followed by a 24 - bit address (a23 - a0) of 000000h , 8 - bit continuous read mode bits, with the capability to input the address bits two bits per clock . after which, the ma nufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edge of clk with most significant bit s (msb) first as shown in figure 3 0 . the device id values for the w25q80bw is listed in manufacturer and device identific ation table. if the 24 - bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is comple ted by driving /cs high. figure 3 0 . read manufacturer / device id dual i/o diagram note: the c ontinuous read mode bits m 7 - 0 must be set to fxh to be compatible with fast read dual i/o instruction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
w25q80bw - 52 - 7.2.33 read manufacturer / device id quad i/o (94h) the rea d manufacturer / device id quad i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 4x speed . the read manufacturer / device id quad i/o ins truction is similar to the fast read quad i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9 4 h followed by a 24 - bit address (a23 - a0) of 000000h , 8 - bit continuous read mode bits and then four clock dummy cycles, with the capability to input the address bits four bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as s hown in figure 3 1 . the device id values for the w25q80bw is listed in manufacturer and device identification table. if the 24 - bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacture r and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 3 1 . read manufacturer / device id quad i/o diagram note: the c ontinuous read mode bits m7 - 0 must be set to fxh to b e compatible with fast read quad i/o instruction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
w25q80bw publication release date: july 30 , 201 3 - 53 - revision j 7.2.34 read unique id number (4bh) the read unique id number instruction accesses a factory - set read - only 64 - bit number that is unique to each w25q80bw device. the id number can be used in conjunction with user s oftware methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followed by a four bytes of dummy clocks. after which, the 64 - bit id is shifted o ut on the falling edge of clk as shown in figure 3 2 . figure 3 2 . read unique id number instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
w25q80bw - 54 - 7.2.35 read jedec id (9fh) for compatibility reasons, the w25q80bw provides several instructions to electronically determine the identity of the devi ce. the read jedec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9fh. the jedec assigned manufac turer id byte for winbond (efh) and two device id bytes, memory type (id15 - id8) and capacity (id7 - id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 3 3 . for memory type and capacity values refer to manufacturer and device identification table. figure 3 3 . read jedec id instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb *
w25q80bw publication release date: july 30 , 201 3 - 55 - revision j 7.2.36 erase security registers (44h) the w25q80bw offers four 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security register instruction is similar to the sector erase instruction . a write enable instruction must be executed before th e device will accept the erase security register instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 44 h followed by a 24 - bit address (a23 - a0) to erase one of the four security register s . address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #0 * 00h 0 0 0 0 0 0 0 0 dont care security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security re gister #3 00h 0 0 1 1 0 0 0 0 dont care * please note that security register 0 is reserved by winbond for future use. it is recommended to use security registers 1 - 3 before using register 0 . the erase security register instruction sequence is shown in f igure 3 4 . the /cs pin must be driven high after the eighth bit of the last byte has been l atched. if this is not done the instruction will not be executed. after /cs is dri ven high, the self - timed erase security register operation will commence for a time duration of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the security register lock bits (lb3 - 0) in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, erase security register instruction to that register will be ignored (see 7.1 .9 for detai l descriptions). figure 3 4 . erase security registers instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q80bw - 56 - 7.2.37 program security registers (42h) the program security register instruction is similar to the page program instruction. it allows from one byte to 256 bytes of security register d ata to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the program security register instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. address a 23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #0 * 00h 0 0 0 0 0 0 0 0 byte address security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address * please n ote that security register 0 is reserved by winbond for future use. it is recommended to use security registers 1 - 3 before using register 0 . the program security register instruction sequence is shown in figure 3 5 . the security register lock bits (lb3 - 0) in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, program security register instruction to that register will be ignored (see 7.1 .9 , 7.2 . 2 1 for detail descriptions). figure 3 5 . program security registers instruction sequence /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q80bw publication release date: july 30 , 201 3 - 57 - revision j 7.2.38 read security registers (48h) the read security register instruction is similar to the fast read instruction and allows one or more data bytes to be sequentially r ead from one of the four security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 48h followed by a 24 - bit address (a23 - a0) and eight dummy clocks into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out . o nce the byte address reaches the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, and continue to increment. the instruction is complet ed by driving /cs high. the read security register instruction sequence is shown in figure 3 6 . if a read security register instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read security register instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #0 * 00h 0 0 0 0 0 0 0 0 byte address security re gister #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address * please note that security register 0 is reserved by winbond for future use. it is recommended to use security registers 1 - 3 before using register 0 . figure 3 6 . read security registers instruction sequence /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q80bw - 58 - 8. electrical character istic s 8.1 absolute maximum ratings ( 1 ) parameters symbol conditions range unit supply voltage vcc C 0.6 to vcc+0.4 v voltage ap plied to any pin v io relative to ground C 0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground C 2.0v to vcc+2.0v v storage temperature t stg C 65 to +150 c lead temperature t lead see note ( 2 ) c electrostatic discharge voltage v esd human body model ( 3 ) C 2000 to +2000 v notes: 1 . this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device re liability. exposure beyond absolut e maximum ratings may cause permanent damage. 2 . compliant with jedec standard j - std - 20c for small body sn - pb or pb - free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu . 3 . jedec std jesd22 - a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 8.2 operating ranges parameter symbol conditions spec unit min max supply voltage (1) vcc f r = 80 mhz f r = 50 mhz (03h & continuous read mode) 1.65 1.95 v ambient temperature, operatin g t a industrial C 40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q80bw publication release date: july 30 , 201 3 - 59 - revision j 8.3 power - up timing and write inhibit threshold parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 .0 1.4 v note: 1. these parameters are characterized only. figure 3 7 . power - up timing and voltage levels figure 37b . power - up, power - down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time
w25q80bw - 60 - 8.4 dc electrical characteristics parameter symbol conditions spec unit min typ max input capacitance c in ( 1 ) v in = 0v ( 1 ) 6 pf output capacitance cout ( 1 ) v out = 0v ( 1 ) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 20 30 a power - down current i cc 2 /cs = vcc, vin = gnd or vcc 7 20 a current read data / dual /quad 1mhz ( 2 ) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 4 / 5 / 6 6/ 7.5/9 ma current read data / dual /quad 33mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 6 / 7/8 9/10.5/12 ma current read data / dual /quad 50 mhz ( 2 ) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 7 / 8/9 10/12/13.5 ma current read data / dual output read /quad outpu t read 80 mhz ( 2 ) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 10 / 11 / 12 15/16.5/18 ma current write status register i cc 4 /cs = vcc 8 20 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il vcc x 0.3 v input high voltage v ih vcc x 0.7 v output low voltage v ol i ol = 1 00 a 0. 2 v output high voltage v oh i oh = C 100 a vcc C 0.2 v notes: 1 . tested on sample basis and specified thro ugh design and characterization data. ta = 25 c, vcc = 1.8 v . 2 . checker board pattern.
w25q80bw publication release date: july 30 , 201 3 - 61 - revision j 8.5 ac measurement conditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vc c to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0. 5 vcc to 0. 5 vcc v note: 1. output hi - z is defined as the point where data out is no longer driven. figure 3 8 . ac measurement i/o waveform input and output timing reference levels input levels 0.8 vcc 0.2 vcc 0.5 vcc
w25q80bw - 62 - 8.6 ac electrical characteristics description symbol alt spec unit min typ max clock frequency for all instructions except read data instruction (03h) f r f c d.c. 80 mhz clock freq uency for read data instruction ( 03h ) & co ntinuous read mode f r d.c. 50 mhz clock high, low time for all instructions except read data (03h) t clh 1 , t cll 1 ( 1) 6 ns clock high, low time for read data (03h) instruction t crlh , t crll ( 1) 8 ns clock rise time peak to peak t clch ( 2) 0.1 v/ns clock fall time peak to peak t chcl ( 2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active ho ld time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read ? array read) t shsl 1 t csh 10 ns /cs deselect time (for erase or program ? read status registers ) volatile status register write time t shsl 2 t csh 50 50 ns output disable time t shqz ( 2) t dis 7 ns clock low to output valid t clqv 1 t v 1 7 ns clock low to output valid (for read id instructions) t clqv 2 t v 2 7.5 ns output hold time t clqx t ho 0 ns /hold active setup tim e relative to clk t hlch 5 ns continued C next page
w25q80bw publication release date: july 30 , 201 3 - 63 - revision j 8.7 ac electrical characteristics ( contd) description symbol alt spec unit min typ max /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 n s /hold not active hold time relative to clk t chhl 5 ns /hold to output low - z t hhqx ( 2) t lz 7 ns /hold to output high - z t hlqz ( 2) t hz 12 ns write protect setup time before /cs low t whsl ( 3 ) 20 ns write protect hold time after /cs high t shwl ( 3 ) 100 ns /cs high to power - down mode t dp ( 2) 3 s /cs high to standby mode without electronic signature read t res 1 ( 2) 3 0 s /cs high to standby mode with electronic signature read t res 2 ( 2) 30 s /cs high to next instruction after suspend t sus ( 2) 20 s write status register time t w 10 15 m s byte program time (first byte) ( 4 ) t bp1 3 0 50 s additional byte program time (after first byte) ( 4 ) t bp2 2.5 12 s page program time t pp 0. 4 0.8 m s sector erase time (4kb) t se 30 200 /4 00 (5) ms block erase time ( 32 kb) t be 1 120 800 ms block erase time (64kb) t be 2 150 1 ,000 ms chip erase time t ce 2 6 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. val ue guaranteed by design and/or characterization, not 100% te sted in production. 3. only applicable as a constraint for a write status register ins truction when srp0 bit is set t o 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed . 5. max value t se with <50k cycles is 200ms and >50k & <100k cycles is 400ms.
w25q80bw - 64 - 8.8 serial output timing 8.9 serial input timing 8.10 /hold timing 8.11 /wp timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl /cs clk io output /hold tchhl thlch tchhh thhch thlqz thhqx io input /cs clk /wp twhsl tshwl io input write status register is allowed write status register is not allowed
w25q80bw publication release date: july 30 , 201 3 - 65 - revision j 9. package spec ification 9.1 8 - pin soic 150 - mil (package code sn) symbol millimeters inches min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.008 0.010 e 3.80 4.00 0.150 0.157 d 4.80 5.00 0.188 0.196 e 1.27 bsc 0.050 bsc h e 5.80 6.20 0.228 0.244 y --- 0.10 --- 0.004 l 0.40 1.27 0.016 0.050 0 10 0 10 e 1 8 5 4 control demensions are in milmeters . ? e
w25q80bw - 66 - 9.2 8 - pin vsop 150 - mil (package code sv) symbol millimeters inches min nom max min nom max a --- --- 0.90 --- --- 0.03 5 a1 0.01 0. 05 --- 0.0004 0.00 2 --- a2 --- 0.80 --- --- 0.031 --- q 0.19 0.20 0.21 0.007 0.008 0.008 b 0.33 --- 0.51 0.013 --- 0.020 c 0.125 bsc 0.005 bsc d 4.80 4.90 5.00 0.189 0.193 0.197 e 5.80 6.00 6.20 0.228 0.236 0.244 e1 3.80 3.90 4.00 0.150 0.154 0.157 e 1.27 bsc 0.050 bsc l 0.40 0.71 1.27 0.016 0.028 0.050 0 --- 10 0 --- 10 notes: 1. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm per side. 2. dimension e1 does not include inter - lead flash or protrusions. inter - lead f lash and protrusions shall not exceed 0.25mm per side.
w25q80bw publication release date: july 30 , 201 3 - 67 - revision j 9.3 8 - pin soic 208 - mil (package code ss) symbol millimeters inches min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0. 075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8
w25q80bw - 68 - 9.4 8 - pin vsop 208 - mil (package code st) symbol millimeters inches min nom max min nom max a D D 1.00 D D 0.0 39 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.75 0.80 0.85 0.030 0.031 0.033 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.127 ref 0.005 ref d 5.18 5.28 5.38 0.204 0.208 0.212 e 7.70 7.90 8.10 0.303 0.311 0.319 e1 5.18 5.28 5.38 0.204 0.208 0.212 e D 1.27 D D 0.050 D l 0.50 0.65 0.80 0.020 0.026 0.031 y D D 0.10 D D 0.004 0 D 8 0 D 8
w25q80bw publication release date: july 30 , 201 3 - 69 - revision j 9.5 8 - pad wson 6x5 - mm (package code zp) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0. 002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.0 08 ref --- d 5.90 6.00 6.10 0.232 0.236 0.240 d2 3.35 3.40 3.45 0.132 0.134 0.136 e 4.90 5.00 5.10 0.193 0.197 0.201 e2 4.25 4.30 4.35 0.167 0.169 0.171 e 1.27 bsc 0.050 bsc l 0.55 0. 60 0.65 0.022 0.024 0.026 y 0.00 --- 0.075 0.000 --- 0.003
w25q80bw - 70 - 8 - pad wson 6x5 - mm contd. symbol millimeters inches min nom max min nom max solder pattern m 3.40 0.13 4 n 4.30 0.169 p 6.00 0.236 q 0.50 0.0 20 r 0.75 0.02 6 notes: 1. advanced packaging information; please contact winbond for the latest minimum and maximum specifications. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusions and should be measured from the bottom of the package. 4 . the metal pad area on the bottom center of the package is connected to the device ground (gnd pin). avoid placement of exposed pcb vias under the pad.
w25q80bw publication release date: july 30 , 201 3 - 71 - revision j 9.6 8 - ball wl bga (package cod e by ) symbol millimeters inches mi n nom max min nom max a w25q80bw byig 0.431 0.472 0.512 0.017 0.019 0.020 a w25q80bw byic 0.471 0.512 0.556 0.019 0.020 0.022 a1 0.152 0.167 0.182 0.006 0.007 0.007 c w25q80bw byig 0.279 0.305 0.330 0.011 0.012 0.013 c w25q80bw byic 0. 31 9 0.3 4 5 0.3 74 0.01 3 0.01 4 0.01 5 d 1.356 1.411 1.436 0.053 0.056 0.057 e 2.316 2.371 2.396 0.091 0.093 0.094 d 1 --- 0.5000 --- --- 0.0197 --- d2 --- 0.4555 --- --- 0.0179 --- d3 --- 0.4555 --- --- 0.0179 --- e1 --- 1.5000 --- --- 0.0591 --- e2 --- 0.4355 --- --- 0.017 1 --- e3 --- 0.4355 --- --- 0.0171 --- b 0.240 0.300 0.360 0.009 0.012 0.014 aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.03 0.001 ddd 0.15 0.006 ee e 0.05 0.002 note: dimension b is measured at the maximum solder bump diameter, parallel to primary datum c.
w25q80bw - 72 - 10. ordering information notes: 1. t he w prefix is not included on the part marking. 2. only the 2 nd letter is used for the part marking. wson package type zp is not used for the part marking. 3. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (sh a pe t) or tray (shape s) , when placing orders. 4. for shipments with otp feature enabled, please specify when placing orders . w ( 1 ) 25q 80b w xx ( 2 ) w = winbond 25 q = s pi flash serial flash me mory with 4 kb sectors, dual /quad i/o 80b = 8m - bit w = 1.65v to 1.95v sn = 8 - pin soic 150 - mil sv = 8 - pin vsop 150 - mil ss = 8 - pin soic 208 - mi l st = 8 - pin vsop 208 - mil zp = 8 - pad wson 6x5 - mm by = 8 - ball wl bga i = industrial ( - 40 c to +85c) g = green pa ckage (lead - free, rohs compliant, halogen - free (tbba), antimony - oxide - free sb 2 o 3 ) p = green package with status register power - down & otp enabled l = special driver strength version for certain applications c = wlbga package with backside coating ( 3,4 )
w25q80bw publication release date: july 30 , 201 3 - 73 - revision j 10.1 valid pa rt numbers and top side marking the following table provides the valid part numbers for the w25q80bw spiflash memory . please contact winbond for specific availability by density and package type. winbond spiflash memories use an 12 - digit product number for ordering. however, due to limited space, the top side marking on a ll packages use an abbreviated 10 - digit number. package type density product number top side marking sn soic - 8 150mil 8m - bit w25q80bw snig w25q80bw sni p w25q80bw sni l 25q 80bw nig 25q 80bw ni p 25q 80bw ni l s v (2) vsop - 8 150mil 8m - bit w25q80bw s v ig w25q80bw s v i p 25q 80bwv ig 25q 80bwv i p ss soic - 8 208mil 8m - bit w25q80bw ssig w25q80bw ssi p 25q 80bw sig 25q 80bw si p s t (2) vsop - 8 208mil 8m - bit w25q80bw s t ig w25q80bw s t i p 25q 80bwt ig 25q 80bwt i p zp (1) wson - 8 6x5mm 8m - bit w25q80bw zpig w25q80bw zpi p 25q 80bw ig 25q 80bw i p by ( 3 ) wlbga - 8 8m - bit w25q80bwby i g w25q80bwby i c 3axx notes: 1. for wson packages, the package type zp is not used in the top side marking. 2. these package types are special order only, please contact winbond for more informatio n . 3. wl bga package type by has special top marking due to size limitation. 3 = 8mb; a = w25q series, 1.8v ; xx = date code (year, work week) . w25q80bwbyic has backside coating.
w25q80bw - 74 - 11. revision h istory version date page description a 01/26/11 all new cre ate preliminary b 0 6 / 2 1 /11 7, 70 - 72 58, 60, 62 65 - 69 added dbga (wlcsp) package type updated icc1/ 2 /4 , fr for continuous read mode updated package dimension drawings c 07/15/11 64 21 - 57 added /wp timing diagram updated all instruction diagrams (non - techn ical) d 11/ 16 /11 5 - 7 , 69 - 71 removed uson package updated package name to wlbga e 04/23/12 6, 66, 68, 72 - 73 added vsop package types f 06/21/12 72 - 73 added l order option g 08/2 4 /12 71 - 73 added wlbga with backside coating order option h 10/ 1 5 /12 all 66 71 removed preliminary designator updated vsop package dimensions updated wlbga package dimensions i 11/19/12 4 5, 46 removed suspend/resume description, added note j 07 / 30 /1 3 59 60 modified the typo of vcc range added power - up, power - down requirement t rademarks winbond and s piflash are trademarks of winbond electronics corporation . all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in sy stems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to suppo rt or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond custo mers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is provided solely in connection with win bond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

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